A typical display system in a computer system has a graphics controller, a frame buffer memory, a display controller and a system controller. The graphics controller may include multiple processors and a frame buffer memory interface coupled to a common bus. The processors may include a display controller, graphics accelerator, system interface and video processor. The processors are coupled to the frame buffer memory through the memory interface. The frame buffer memory is constructed using a DRAM array and has a capacity to store pixel data for at least one frame of a video display image. The processors and memory interface are usually integrated on a single chip. The performance of such a display system is usually limited by the bandwidth of the frame buffer memory.
In the literature a “unified memory system” usually refers to the graphics memory being integrated with the system memory. A better term here is a “unified graphics memory”. One prior art computer system uses a unified graphics memory system, which contains two color buffers. One of the color buffers is a display buffer and the other is a render target buffer. There also may be a Z buffer. All buffers are stored in a common memory. This results in significant cost since the memory must have a high bandwidth. Another prior art computer system uses a separate memory for each type of buffer, that is a front buffer memory, a back buffer memory, a texture buffer memory and a Z buffer memory, for example. Such a prior art system has increased complexity, and less flexibility, especially in tradeoffs between the bandwidth needed for color vs. the bandwidth needed for Z values.
In historical systems the display refresh was the largest user of bandwidth, and there are prior art methods that increase the available bandwidth in a single memory (dual port VRAM). These systems were characterized by high resolution, but very low update rates “interactive” graphics of as many as 10 frame per second, but more likely several seconds per frame. Modem real-time graphics systems have applications where the update rate of the screen is close to the refresh rate of the monitor, furthermore each pixel on the render target may be drawn several times as layers of the image are drawn. For these applications, that now are the majority of the applications for computer graphics hardware, the refresh bandwidth is a fraction of the rendering bandwidth.
The use of either one common memory or a separate memory for each buffer are drawbacks of the prior art that result in inefficient operation and/or costly implementations of the computer systems